📋 Complete Advertisement & Guidelines
IIT Hyderabad (IITH) has released a recruitment notification for the position of Analog Layout Engineer. This opportunity is available on a full-time contract basis within the R&D project at DARMIC LAB. Candidates with a B.Tech in ECE and relevant experience in analog layout are encouraged to apply before the deadline.
| Company | Indian Institute of Technology Hyderabad (IITH) |
| Post Name | Analog Layout Engineer |
| Total Vacancies | 3 |
| Last Date | 25 January 2026 |
| Job Location | IIT Hyderabad, DARMIC LAB |
| Official Website | https://www.iith.ac.in/ |
Vacancy Details
| Post Name | No. of Posts | Salary | Project / Department |
|---|---|---|---|
| Analog Layout Engineer | 3 | 10,000 INR per month | R&D Project at DARMIC LAB |
Eligibility Criteria
Eligibility for Analog Layout Engineer
- Essential Qualification: B.Tech – ECE.
- Experience: Looking for a fresher trainee with 6 months / 1+ years of experience.
- Preferred Skills:
- Experience in using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre verification tool (Assura and/or Hercules is a plus).
- Knowledge of various Analog Layout Techniques.
- Understanding of circuit principles as affected by layout such as speed, capacitance, power, noise, and area.
- Ability to exchange and communicate information with Analog Designers and team members.
- Possess good team building skills.
- Excellent communication, documentation, and presentation skills.
- Key Responsibilities:
- Work on custom layout Analog IPs like PLL, ADCs, DACs, Voltage Reference Generators, High-speed IOs, and custom layout of standard cells.
- Performing verification checks like DRC/LVS/Antenna and fixing violations.
- Work closely with the design engineers and layout engineers in designing and successfully delivering Analog Layouts.
- Need to work and review layouts which produces good yield.
- Performing various kinds of Analog Layouts, implementations from top-level floor planning down to complex block level layouts.
Important Links
- Apply Online: Send Resume to [email protected]
- Official Notification PDF: Click Here to Download
- Official Website: https://www.iith.ac.in/
FAQs
Q1: What is the last date to apply for IIT Hyderabad Analog Layout Engineer recruitment?
A: The last date to receive the CV is 25th January 2026.
Q2: What is the salary for the Analog Layout Engineer post?
A: The salary is 10,000 INR per month.
Q3: What is the required qualification?
A: Candidates must have a B.Tech in ECE with 6 months to 1+ years of experience.
Q4: How to apply for this position?
A: Candidates need to drop their latest resume at [email protected] on or before 25th January 2026.