๐Ÿ›๏ธ National Institute of Electronics and Information Technology New Delhi Contractual / Project-Based (Tenure)
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NIELIT VLSI Design Recruitment 2026 - Walk-in Interview, Eligibility, Salary

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Recruitment Fact-Sheet & Key Specifications

Official recruitment summary for candidates and search engines.

Verified Notification Data
๐Ÿ‘ฅ
Total Vacancies
02 Posts
๐Ÿ’ฐ
Salary / Remuneration
๐Ÿ“ฎ
Selection / Apply Mode
Direct Walk-in
โฐ
Interview Date
25 February 2026
๐Ÿ›๏ธ 1. Conducting Organization National Institute of Electronics and Information Technology New Delhi ๐Ÿ“‘ 2. Advertisement Reference No. NIELIT/NOIDA/CoE/2026/04
๐Ÿ’ผ 3. Nature of Employment Contractual / Project-Based (Tenure) ๐ŸŽฏ 4. Exact Post & Vacancy Count VLSI Design Expert, Junior VLSI Engineer (02 Posts)
๐Ÿ“ฎ 5. Application / Selection Mode Online / Offline No Prior Online Reg. Required ๐Ÿ“… 6. Crucial Dates & Timings 25 February 2026
โฐ Reporting Time: 10:00 AM
๐Ÿ“ 7. Exact Physical Venue / Address
.
๐Ÿ’ต 8. Application Fee Deposit
๐ŸŽ“ Eligibility & Qualification Refer Official Notification ๐ŸŒ Authority Official Website www.nielit.gov.in ↗
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๐Ÿ“‹ Candidate Walk-in Interview Checklist

Candidates must verify and arrange the following documents in chronological order prior to reporting to the interview venue:

โœ… Bio-data / Proforma: Duly completed, signed application form (per notification format).
โœ… Original Certificates: 10th / Matriculation (DOB proof), Essential Degrees & Marksheets.
โœ… Self-Attested Photocopies: Two complete sets of photocopies of all relevant testimonials.
โœ… Passport Photographs: 2 to 4 recent passport-size colour photographs (same as bio-data).
โœ… Valid Photo ID Proof: Original Aadhaar Card, Voter ID, Passport, or PAN Card.
โœ… Experience & NOC: Experience certificates and "No Objection Certificate" if currently employed.

๐ŸŽฏ Selection Methodology, Screening Contingency & Perks

๐Ÿ“ Preliminary Screening Test Clause (Turnout Contingency)

In the event of a disproportionately high candidate turnout for the walk-in interview, the competent committee reserves the discretionary right to conduct an objective preliminary written / screening test to shortlist candidates before calling them for personal interview.

๐Ÿš† Traveling Allowance / Dearness Allowance (TA/DA) Disclosure

No TA/DA will be paid or admissible to any candidate for attending the walk-in interview. Candidates are required to make their own arrangements for travel, boarding, and lodging.

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๐Ÿ“‹ Complete Advertisement & Guidelines

NIELIT VLSI Design Recruitment 2026 - Walk-in Interview, Eligibility, Salary

NIELIT Recruitment 2026: Walk-in for VLSI Design Expert/ Junior VLSI Engineer

The National Institute of Electronics and Information Technology (NIELIT), Centre of Excellence in Chip Design, Noida, has released an official notification (Advt No. NIELIT/NOIDA/CoE/2026/04) for the recruitment of 02 posts of VLSI Design Expert and Junior VLSI Engineer. This is a direct recruitment drive based on a Walk-in-Interview.

This is an excellent opportunity for candidates with a background in Electronics, Electrical Engineering, or VLSI Design to work with a premier government institute focused on chip design. The position offers a consolidated salary of Rs. 40,000/- per month.

Recruitment Type

Direct Recruitment (Walk-in-Interview): This recruitment does not involve a written competitive examination. Selection is based on Document Verification and a Personal Interview.

Key Highlights Table

Feature Details
Organization Name National Institute of Electronics and Information Technology (NIELIT)
Post Name(s) VLSI Design Expert, Junior VLSI Engineer
Total Vacancies 02
Interview Date 25-02-2026
Interview Location NIELIT COE Noida, PS-1D, Behind Brahmaputra Shopping Complex, Sector-29, Noida, 201303
Official Website http://coenoida.in

Vacancy Details

Post Name Total Vacancies
VLSI Design Expert / Junior VLSI Engineer 02
Total 02

Eligibility Criteria

1. Educational Qualification

  • Option A: Masterโ€™s Degree in Electronics & Communication, Electrical Engineering, VLSI Design, or related field from a recognized University/Institute.
  • Option B: Bachelorโ€™s Degree in Electronics & Communication, Electrical Engineering, VLSI Design, or related field PLUS Two years of relevant experience.

2. Age Limit

  • Maximum Age: 45 Years
  • Age as on: 25-02-2026 (Candidates must ensure they meet the age criteria as of the date of the interview).

3. Mandatory Requirements

  • Experience: For candidates with a Bachelorโ€™s degree, 2 years of experience is mandatory.
  • Documents: Candidates must bring all original educational and experience certificates for verification.

Selection Process

Since this is a Walk-in-Interview recruitment, the selection process involves the following stages:

  1. Document Verification: Verification of original certificates (Educational, Experience, Caste, etc.).
  2. Walk-in-Interview: Personal interview to assess technical knowledge and suitability for the role.

Application Fee

Category Fee Amount
General / OBC / EWS Rs. 500/-
Payment Mode Online deposit to NIELIT Gorakhpur Punjab National Bank Account.

Bank Details:
Account No: 1914002100094252
IFSC: PUNB0191400

How to Apply (Step-by-Step Guide)

Eligible candidates must follow these steps to attend the Walk-in-Interview:

  1. Check Eligibility: Ensure you meet the educational and age criteria mentioned above.
  2. Pay Application Fee: Deposit Rs. 500/- online using the bank details provided above.
  3. Download Application Form: Download the prescribed Application Form from the Official Website or the link provided below.
  4. Fill the Form: Complete the application form with accurate details and paste a recent passport-sized photograph.
  5. Prepare Documents: Gather self-attested copies of educational certificates, experience certificates, fee receipt, and the filled application form.
  6. Attend Interview: Report for the Walk-in-Interview on the specified date and venue.
  7. Venue:
    NIELIT COE Noida
    PS-1D, Behind Brahmaputra Shopping Complex
    Sector-29, Noida, 201303
    Date: 25-02-2026
    Reporting Time: 10:00 AM (Candidates are advised to arrive early).

Important Dates

  • Walk-in-Interview Date: 25-02-2026
  • Document Verification: 25-02-2026
  • Last Date to Apply/Check Notification: 25-02-2026

Important Links