📋 Complete Advertisement & Guidelines
NIT Uttarakhand Recruitment 2026 for Junior Research Fellow and Research Associates
Exciting opportunity for candidates with M.E/M.Tech/M.S or Ph.D degrees at the National Institute of Technology, Uttarakhand. The institute is conducting a walk-in interview for various research positions under the Chips to Startup (C2S) Programme. Candidates with strong technical skills in biomedical signal acquisition, VLSI design, and machine learning algorithms are encouraged to apply.
| Company Name | National Institute of Technology, Uttarakhand (NIT Uttarakhand) |
|---|---|
| Posts Offered | Junior Research Fellow, Research Associate-I, II, III |
| Total Vacancies | 04 (01 per post) |
| Last Date to Attend Walk-in | 23 February 2026 (Monday) |
| Official Website | nituk.ac.in |
Vacancy Details
| Post Name | Number of Posts | Salary (per month) | Project |
|---|---|---|---|
| Junior Research Fellow | 01 | Rs. 38,000/- + HRA | Chips to Startup (C2S) Programme |
| Research Associate – I | 01 | Rs. 58,000/- + HRA | Chips to Startup (C2S) Programme |
| Research Associate – II | 01 | Rs. 61,000/- + HRA | Chips to Startup (C2S) Programme |
| Research Associate - III | 01 | Rs. 67,000/- + HRA | Chips to Startup (C2S) Programme |
Note: The institute may decide the specific level for Research Associates based on experience.
Eligibility Criteria
Eligibility for Junior Research Fellow
- Essential Qualification: M.E/M.Tech/M.S in Electronics and Communication Engineering, Biomedical Engineering, Digital Signal Processing, Signal Processing, or allied areas with minimum 1st class in B.E/B.Tech & M.E/M.Tech.
- Additional Requirement: GATE/NET qualification is mandatory.
- Experience: Not specified.
- Age Limit: Preferably below 35 Years.
Eligibility for Research Associate – I
- Essential Qualification: Ph.D in Microelectronics & VLSI Design or Signal Processing, OR M.E/M.Tech having 3 years of research experience with at least one research paper in SCI/SCIE Journal. Specialization must be in Design and Development of Instrumentation Amplifier for EEG Signal Acquisition or FPGA implementation of EEG Signal Processing, Machine Learning, and Deep Learning Algorithms.
- Experience: Required (3 years for M.E/M.Tech candidates).
- Age Limit: Not specified.
Eligibility for Research Associate – II
- Essential Qualification: Ph.D in Microelectronics & VLSI Design or Signal Processing, OR M.E/M.Tech having 3 years of research experience with at least one research paper in SCI/SCIE Journal. Specialization must be in Design and Development of Instrumentation Amplifier for EEG Signal Acquisition or FPGA implementation of EEG Signal Processing, Machine Learning, and Deep Learning Algorithms.
- Experience: Required (3 years for M.E/M.Tech candidates).
- Age Limit: Not specified.
Eligibility for Research Associate - III
- Essential Qualification: Ph.D in Microelectronics & VLSI Design or Signal Processing, OR M.E/M.Tech having 3 years of research experience with at least one research paper in SCI/SCIE Journal. Specialization must be in Design and Development of Instrumentation Amplifier for EEG Signal Acquisition or FPGA implementation of EEG Signal Processing, Machine Learning, and Deep Learning Algorithms.
- Experience: Required (3 years for M.E/M.Tech candidates).
- Age Limit: Not specified.
Job Role and Skill Requirements
- Strong knowledge in Circuit Design for Biomedical Signal Acquisition and EDA Tools.
- Strong knowledge in implementation of EEG Signal Processing and Machine/Deep learning algorithms in Python/MATLAB and FPGA.
- Good Technical and Communication Skills.
Important Links
FAQs
Q1: What is the last date to attend the walk-in interview?
A: The walk-in interview is scheduled for 23 February 2026 (Monday). Reporting time is 1:00 PM to 2:30 PM.
Q2: Is GATE/NET mandatory for all posts?
A: GATE/NET is mandatory only for the Junior Research Fellow post. For Research Associate positions, a Ph.D or specific research experience is required.
Q3: What is the application process?
A: Candidates must appear physically for the walk-in interview at Committee Room (C106), Department of Electronics Engineering, NIT Uttarakhand, Srinagar Campus. They must also send an advance copy of the application form to [email protected].