IIT Patna Junior Research Fellow Recruitment 2026 - Notification, Eligibility, Salary

Recruitment Overview

The Indian Institute of Technology Patna (IIT Patna) has released an official notification for the recruitment of 01 Junior Research Fellow (JRF) posts. This recruitment is for the project titled "ML Enabled RISC-V based i-LoRa SOC for Forest Event Monitoring," funded by the Ministry of Electronics and Information Technology (MeitY), Delhi under the C2S Programme.

This is a Competitive Examination recruitment process involving a Written Test followed by a Personal Interview. It is a research project position offering an excellent opportunity for candidates with a strong background in VLSI, Embedded Systems, and Machine Learning to work on advanced technology.

Key Highlights

Vacancy Details

Note: The position is initially for 2 years as JRF and may be extended as SRF based on performance.

Eligibility Criteria

Educational Qualification

Candidates must possess any one of the following qualifications:

• Option 1 (M.Tech): M.Tech in VLSI/Embedded System/Microelectronics/Electronics System/Communication System/Instrumentation/Computer Science Engineering with minimum CPI 6.5 or 60% marks. Must have qualified GATE within the last 5 years.
• Option 2 (B.Tech/B.E.): B.Tech/B.E./B.Sc(Engg.) in Electrical/Electronics/Communication/Instrumentation/Computer Science & Engineering with minimum CPI 7.5 or 70% marks. Must have qualified GATE within the last 5 years.
• Option 3 (M.Sc): M.Sc in Physics/Mathematics/Electronics/Instrumentation. Must have qualified GATE or CSIR-NET within the last 5 years.

Age Limit

As per IIT Patna norms and DST guidelines (usually up to 28 years for JRF). However, specific upper age limits are not explicitly mentioned in the text; candidates should refer to the official notification PDF for exact relaxation rules.

Desirable Qualifications

• Experience in VLSI design, Embedded systems, or RISC-V architecture.
• Knowledge of IoT and LoRa communication protocols.
• Background in Machine Learning and signal processing.
• Experience with HDL programming (Verilog/VHDL).
• Familiarity with edge computing platforms.

Selection Process & Exam Structure

This recruitment follows a Competitive Examination process consisting of two stages:

1. Written Test: A technical written test will be conducted to assess domain knowledge.
2. Personal Interview: Candidates shortlisted from the written test will appear for an interview.

Exam Pattern (Written Test)

Syllabus Highlights

• VLSI Design: Digital Logic, CMOS, Verilog/VHDL.
• Embedded Systems: Microcontrollers, RTOS, IoT protocols.
• Machine Learning: Basics of ML algorithms and signal processing.
• Communication: LoRa technology, wireless communication basics.

Application Fee

There is no application fee mentioned for this recruitment.

How to Apply (Step-by-Step)

1. Download Form: Download the application form (Form No. RD-M003) from the official notification (Download Link).
2. Fill Application: Fill the form completely with all required details.
3. Prepare Documents: Scan the following documents into a single file (PDF preferred):
   • Completed application form (RD-M003).
   • GATE Score Card (qualified within last 5 years).
   • Resume highlighting relevant exposure (VLSI, ML, IoT).
   • Educational qualification certificates and mark sheets.
4. Send Email: Send the combined document via email to [email protected].
5. Subject Line: Use the subject: "Application for JRF - R&D/908/MEM/540".
6. Deadline: Ensure submission before 17.02.2026.

Important Dates

Important Links

• Official Notification PDF: Click here to Download
• Official Website: Click here